A Binary Width-demodulated Pulse Rebalance Loop Based on FPGA

doi:10.3969/j.issn.1674-5558.2017.02.013

WANG Yong-tong, ZHU Zhi-gang, ZHANG Pei-han, WANG Long

Navigation and Control ›› 2017, Vol. 16 ›› Issue (2) : 69-76.

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Navigation and Control ›› 2017, Vol. 16 ›› Issue (2) : 69-76. DOI: 10.3969/j.issn.1674-5558.2017.02.013

Instrument and Circuit

A Binary Width-demodulated Pulse Rebalance Loop Based on FPGA

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2017, 16(2): 69-76 https://doi.org/10.3969/j.issn.1674-5558.2017.02.013

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Received	Published
2016-03-18	2017-04-05
Issue Date
2020-05-15

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